Nowadays the realization of integrated circuits (IC) to high performances provides the use of digital structures in CMOS (Complementary Metal Oxide Semiconductor) technology.
In fact, such structures allow obtaining low power dissipation, high speeds and a considerable saving of area on chip.
All digital systems base the most of their working on combinational logic circuits, that is circuits having the property that at any point in time, the output of the circuit is related to its current input signals by some Boolean expression.
There are numerous circuit styles to implement a given logic function, each of which presents advantages and disadvantages, which mark it from the others.
These logic families can be divided mainly into two categories: static logic families and dynamic logic families. The Complementary CMOS logic, the pseudo-NMOS logic, the pass-transistor and the transmission gate logics belong to the first group. The dynamic logic with pre-charge phase, for example, belong to the second group.
The Complementary CMOS logic uses NMOS and PMOS exploiting their duality. The generic gate realized through Complementary CMOS logic presents the structure shown in FIG. 1, where the pull-up network (PUN) is a network formed by only PMOS, while the pull-down network (PDN) is a network formed by only NMOS.
Although the Complementary CMOS logic allows to have output logical levels of 0V e VDD (supply voltage) and wide noise margins and static power dissipation almost null, there are however disadvantages, such as the number of transistor required to implement a single gate is very high (2N MOSFET for a N fan-in logic gate), the propagation delay deteriorates rapidly as a function of the fan-in, big intrinsic capacitances whether incoming or outgoing are present.
The pseudo-NMOS logic, whose generic gate is shown in FIG. 1.(b), is attempt to reduce the number of transistors required to implement a given logic function with respect to the Complementary CMOS logic, replacing the pull-up network with a single pMOS transistor.
However, as consequence of the transistors reduction we have a low logical level that is different from 0V, the noise margins decrease and the static power dissipation become quite big.
Another type of logic style alternative to the Complementary CMOS one is the pass-transistor logic, which uses every transistor as one logic gate with two inputs.
The advantage of this structure, in addition to the static power dissipation almost null, is the use of “2(N−2)” transistors for one gate with N fan-in. However, the logic pass-transistor suffers of some drawbacks, including the high logical level is different from the supply voltage and the output of a gate realized through pass-transistor logic cannot drive the gate terminal of a MOSFET, the connection in series of pass-transistor logical gates is limited because this kind of gate does not enjoy the regenerative property; furthermore every gate needs also of some denied inputs.
In the dynamic logic with pre-charge (for example, with high pre-charge as that one illustrated in FIG. 4), only N+2 transistors are used to build a logic gate with N inputs, succeeding anyway to obtain logical output levels of 0V and VDD (supply voltage), a static power dissipation almost null, and low propagation times. The dynamic logic with pre-charge, however, has one of the two noise margins very small and a dynamic power dissipation higher than that one of the Complementary CMOS.
Furthermore, the dynamic logic with pre-charge is very sensitive to the capacitive couplings, because they can alter the output value “during the evaluation phase”. Finally the operation frequency of these logic gates have a lower limit, since the leakage currents which tend to change the quantity of charge stored in the parasitic output capacitor even when it is in high impedance state.